Improved Fused Floating Point Add-Subtract Unit Architecture
نویسنده
چکیده
Floating purpose is that the most vital a part of several fashionable chip. The amalgamate floating-point add–subtract unit is helpful for digital signal process (DSP) applications like quick Fourier rework (FFT) and separate circular function rework (DCT) butterfly operations. IEEE 754 normal specifies the ways for binary and decimal floating purpose arithmetic unit. Moreover, single preciseness addition and subtraction is performed by normalisation. The projected styles square measure enforced for each single preciseness and synthesized with a 45-nm standard-cell library. From the planning the twin path add-subtract unit is developed.
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Improved Architectures for Fused Floating Point Add-Subtract Unit
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